With the continued emphasis on highly integrated electronic devices, there is an ongoing need for semiconductor memory devices that operate at higher speeds and lower power and that have increased device density. To accomplish this, devices with aggressive scaling and multiple-layered devices with transistor cells arranged in horizontal and vertical arrays have been under development.
In one approach, planar memory cells, for example NAND memory cells, are formed in a conventional horizontal, or planar, array. Multiple horizontal arrays are then stacked in a vertical direction, resulting in a three-dimensional device configuration.
In the conventional planar NAND memory configuration, memory cells are arranged in a high-density array in a memory cell region of the device, and peripheral transistors of relatively lower density are arranged in a peripheral region of the device. The memory cells and peripheral transistors are arranged on the device substrate in regions of the substrate referred to as wells, which are regions that are doped with a particular type of impurity.
In the memory cell region, the memory cells are positioned on the substrate in a pocket well that surrounds the memory cells; the pocket well is in turn positioned in a deep well. In an example where the substrate is a p-type substrate, the deep well can be n-type, and the pocket well can be p-type. At the same time, in the peripheral circuit region, the peripheral transistors are positioned on the substrate in a peripheral well, which can be n-type or p-type. Combining the pocket well and deep well in the memory cell region and the peripheral well in the peripheral region, such a well configuration is referred to as a “triple well” configuration.
During a program or erase operation of a non-volatile memory device, a high voltage is typically applied to the pocket well in the memory cell region of the device. The peripheral region must therefore be isolated from the memory cell region during this operation in order to avoid interference with the peripheral region during the program or erase operation, since the memory region and peripheral region share a common substrate. The presence of the deep well in the memory cell region provides this isolation function.
With the desire for increased density in electronic devices, formation of multiple-layered devices continues to become more attractive to semiconductor manufacturers. However, the need for a deep well in the memory cell region of each layer can increase manufacturing costs and can limit device density in the vertical direction of a multiple-layered device.